1. Patent # 7,583,530    Multi-Bit Memory Technology (MMT) and Cells.  (Filed: 10/2/2006        Issued:  9/2009)
   
   The above patent 3 discusses the method and structures for storing more than one bit in a cell – at differing locations using non-spreading storage medium. Multi-bit storage in a single memory cell is become the norm in the industry. The use of a Nitride layer or a silicon-nodule layer or similar layers capable of location specific charge storage with no spreading, allows easy implementation of multi-bit technology. If the charge is stored in the traps in the Nitride storage layer, a Oxide Nitride Oxide is used as the storage element. If charge is stored in layer of discrete silicon-nodules separated by a thin insulating film, an Oxide silicon-nodule Oxide storage element is used as the storage layer. The exemplary multi-bit cells proposed are programmed by hot electron programming and erased either by using high Voltage tunneling, or by use of a lower voltage MIM Metal-Insulator-Metal Diode carrier generation method and technology called the Tunnel-Gun or TG.
    

2. Patent # 7,224,620    CACT-TG (CATT) Low Voltage NVM Cells.   (Filed: 8/18/2006         Issued: 5/2007)
    

3. Patent # 7,193,900    CACT-TG (CATT) Low Voltage NVM Cells.    (Filed: 1/18/2005         Issued: 5/2007)
   
   These applications 2 and 3 are applications that cover structure and methods of program and erase based on the CACT and TG Program erase methods for programming and erasing of a non-volatile memory cell. The typical cell described in the example uses the “Channel Accelerated Carrier Tunneling (CACT) method for programming memories”(US patent # 5,519,653 ), which is herby incorporated by reference,  and structural configuration similar to  “Channel Accelerated Tunneling Electron Cell with a Select Region Incorporated for high density low power applications” (US Patent #5,675,161) and “Double Poly Trenched Channel Accelerated Tunneling Electron (DPT-CATE) cell, for memory applications” (US Patent #5,506,431) for accumulating one type of carriers in the floating gate, and another novel method, the Tunnel Gun (Tun-Gun or TG) method  ( US Patents # 6,479,863 B2, US Patent # 6,384,816 B1, and US patent # 6,534,816 B1) for accumulating the other type of carriers in the floating gate of the cells. These methods both require low applied voltages to achieve positive or negative charge accumulation in the floating gate of Non-Volatile Memory cell. The proposed CAcT-Tg or (CATT) cells due to elimination of high voltage requirements are more scalable with the technology and manufacturable easily using currently available process.   These program/ erase methods and cells reduce the requirement of high voltages and currents that are needed for the present day Non-Volatile memory programming. They also provide the ability to have multi-bit storage capability for the cell by providing self-limiting program erase methods. They in addition reduce the complexity of processing of the cells by reducing the high voltage requirements of the junctions in the cell and periphery. Another advantage is the increase in reliability of Cells using this method due to reduced voltage stress.

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1. Patent # 5,506,431    Double Poly Trenched Channel Accelerated Tunneling Electron (DPT-CATE) Cell, For Memory Applications.   (Filed: 5/16/1994          Issued: 4/1996)
    

2. Patent # 5,519,653    Channel Accelerated Carrier Tunneling-(CACT) Method For Programming Memories.  (Filed: 3/11/1994          Issued: 5/1996)
   
   Patents 8 and 9 are for low voltage programming applications where the acceleration of the carriers are used to reduce the voltage needed overcome the potential barrier. The patent 8, is the method patent for channel accelerated carrier tunneling method is disclosed and patent application 9 is an application of the method within the NVM to achieve low voltage high speed programming of the cells.