Airplane Friendly Touchpad

LOT AT-1

1. Patent # 8,502,790 Touchpad with Reverse-Mounted Buttons. (Filed: 3/30/2010 Issued: 8/6/2013)
   
   Solves the problem of jabbing your neighbor when using a laptop computer on an airplane. A touchscreen laptop can solve the problem, however only recently do some laptops come with touchscreens. At the same time, well over a billion laptops are in use worldwide. The conventionally-located touchpad on a laptop computer causes the user's arm to stick out to the side with their elbow poking their neighbor. This is especially apparent when the space in front of the user is minimal, and even more so when the person seated in front reclines their seat. US patent 8,502,790 attaches a separate assembly to the edge of the laptop's screen. The assembly contains a touchpad on the reverse side facing away from the user, with the associated “mouse buttons” on the front side and facing the user. The user operates the touchpad and buttons with one hand while their arm extends forward, thus avoiding their neighbor.
    

2.  Patent Application #13/769,358 Reverse Touchpad for Portable Computers. (Filed: 2/17/2013)
   
   Pending Continuation Application of 12/750,553 with priority date of 3/10/2010, and solves the problem when a user purchases a laptop with an integral "reverse touchpad".

Browser Performance Enhancement

LOT VW-1

1. Patent No. 7,694,008 METHOD AND APPARATUS FOR INCREASING PERFORMANCE OF HTTP OVER LONG-LATENCY LINKS
   
   The invention increases performance of HTTP over long-latency links by pre-fetching objects concurrently via aggregated and flow-controlled channels. An agent and gateway together assist a Web browser in fetching HTTP contents faster from Internet Web sites over long-latency data links. The gateway and the agent coordinate the fetching of selective embedded objects in such a way that an object is ready and available on a host platform before the resident browser requires it. The seemingly instantaneous availability of objects to a browser enables it to complete processing the object to request the next object without much wait. Without this instantaneous availability of an embedded object, a browser waits for its request and the corresponding response to traverse a long delay link.

 

1. Patent No. 7,860,997 METHOD AND APPARATUS FOR OPTIMIZED FLOW CONTROL TO INCREASE THE PERFORMANCE OVER LONG-LATENCY LINKS
   
   The invention increases performance of HTTP over long-latency links by pre-fetching objects concurrently via aggregated and flow-controlled channels. An agent and gateway together assist a Web browser in fetching HTTP contents faster from Internet Web sites over long-latency data links. The gateway and the agent coordinate the fetching of selective embedded objects in such a way that an object is ready and available on a host platform before the resident browser requires it. The seemingly instantaneous availability of objects to a browser enables it to complete processing the object to request the next object without much wait. Without this instantaneous availability of an embedded object, a browser waits for its request and the corresponding response to traverse a long delay link.

 

1. Patent No. 7,860,998 METHODS AND APPARATUS TO INCREASE THE EFFICIENCY OF SIMULTANEOUS WEB OBJECT FETCHING OVER LONG-LATENCY LINKS
   
   The invention increases performance of HTTP over long­ latency links by pre-fetching objects concurrently via aggregated and flow-controlled channels. An agent and gateway together assist a Web browser in fetching HTTP contents faster from Internet Web sites over long-latency data links. The gateway and the agent coordinate the fetching of selective embedded objects in such a way that an object is ready and available on a host platform before the resident browser requires it. The seemingly instantaneous availability of objects to a browser enables it to complete processing the object to request the next object without much wait. Without this instantaneous availability of an embedded object, a browser waits for its request and the corresponding response to traverse a long delay link.

 

1. Patent No. 7,945,692 METHOD AND APPARATUS FOR INCREASING PERFORMANCE OF HTTP OVER LONG-LATENCY LINKS
   
   The invention increases performance of HTTP over long latency links by pre-fetching objects concurrently via aggregated and flow-controlled channels. An agent and gateway together assist a Web browser in fetching HTTP contents faster from Internet Web sites over long-latency data links. The gateway and the agent coordinate the fetching of selective embedded objects in such a way that an object is ready and available on a host platform before the resident browser requires it. The seemingly instantaneous availability of objects to a browser enables it to complete processing the object to request the next object without much wait. Without this instantaneous availability of an embedded object, a browser waits for its request and the corresponding response to traverse a long delay link.

 

1. Patent No. 8,010,693 METHODS AND APPARATUS TO INCREASE THE EFFICIENCY OF A WEB BROWSER OVER LONG-LATENCY LINKS
   
   The invention increases performance of a browser over long latency links by smart pre-fetching of selective objects to increasing the level of concurrency in subsequent operations. A Web browser with a pre-fetch agent can speed up Internet transactions from the browser over long-latency data links. This agent can help determine the order of fetching objects in such a way that an object is ready and available locally before the resident browser requires it. The seemingly instantaneous availability of objects to a browser enables it to complete processing the object to request the next object without much wait. Without this instantaneous availability of an embedded object, a browser waits for its request and the corresponding response to traverse a long delay link.

 

1. Patent No. 8,108,457 METHODS AND APPARATUS TO ENHANCE THE PERFORMANCE OF WEB BROWSERS OVER BANDWIDTH CONSTRAINED LINKS
   
   Increasing the performance of a browser while operating over bandwidth constrained links by pre-fetching of web objects to increase the level of concurrency. Using an agent or a gateway to speed up its Internet transactions over bandwidth con­ strained connections to source servers. Assisting a browser in determining the order of fetching objects in such a way that an object is ready and available locally before the browser requires it. Providing seemingly instantaneous availability of objects to a browser, enabling it to complete processing the object, to request the next object without much wait.

 

1. Patent No. 8,296,353 FLOW CONTROL METHOD AND APPARATUS FOR ENHANCING THE PERFORMANCE OF WEB BROWSERS OVER BANDWIDTH CONSTRAINED LINKS
   
   Flow control is applied to increasing the performance of a browser while pre-fetching Web objects while operating over bandwidth constrained links to increase the level of concurrency, thus reducing contention for limited bandwidth resources with increased levels of concurrency. Using an agent or a gateway to speed up its Internet transactions over bandwidth constrained connections to source servers. Assisting a browser in the fetching of objects in such a way that an object is ready and available locally before the browser requires it, without suffering congestion on any bandwidth constrained link. Providing seemingly instantaneous availability of objects to a browser, enabling it to complete processing the object, to request the next object without much wait.

 

1. Patent No. 9,043,389 FLOW CONTROL METHOD AND APPARATUS FOR ENHANCING THE PERFORMANCE OF WEB BROWSERS OVER BANDWIDTH CONSTRAINED LINKS
   
   Flow control is applied to increasing the performance of a browser while pre-fetching Web objects while operating over bandwidth constrained links to increase the level of concurrency, thus reducing contention for limited bandwidth resources with increased levels of concurrency. Using an agent or a gateway to speed up its Internet transactions over bandwidth constrained connections to source servers. Assisting a browser in the fetching of objects in such a way that an object is ready and available locally before the browser requires it, without suffering congestion on any bandwidth constrained link. Providing seemingly instantaneous availability of objects to a browser, enabling it to complete processing the object, to request the next object without much wait.

Electro-Optical Modulator

LOT EO-1

1. Patent # 8,044,835 Linearized Optical Digital-to-Analog Modulator. (Filed: 12/14/2009 Issued: 10/25/2011)
   
    

2. Patent # US 8,797,198 LINEARIZED OPTICAL DIGITAL-TO-ANALOG MODULATOR (Filed: 10/25/2011 Issued: 8/5/2014)
   
    

3. Patent # US 9,031,417 LINEARIZED OPTICAL DIGITAL-TO-ANALOG MODULATOR (Filed: 7/8/2014 Issued: 5/12/2015)
   
    

4. Patent # US 9,203,425 LINEARIZED OPTICAL DIGITAL-TO-ANALOG MODULATOR (Filed: 3/19/2015 Issued: 12/1/2015)
   
    

5. Patent # US 9,479,191 LINEARIZED OPTICAL DIGITAL-TO-ANALOG MODULATOR Filed: 10/25/2015 Issued: 10/25/16)

 

1. Patent # EP2174185 System and method for converting digital data into an analogue intensity-modulated optical signal (Filed: 6/12/2008 Issued: 3/23/2015)

 

1. Patent # 10,205,527 LINEARIZED OPTICAL DIGITAL-TO -ANALOG MODULATOR (Filed: 10/20/16 Issued: 2/12/2019)
    

2. Patent # 10,033,465 LINEARIZED OPTICAL DIGITAL-TO -ANALOG MODULATOR (Filed: 10/20/16 Issued: 7/24/2018)
    

3. Patent # 10,270,535 LINEARIZED OPTICAL DIGITAL-TO -ANALOG MODULATOR (Filed: 12/28/18 Issued: 4/23/2019)

4. Patent # 10,461,866 LINEARIZED OPTICAL DIGITAL-TO -ANALOG MODULATOR (Filed: 4/17/19 Issued: 10/29/2019)

5. Patent Application #16/532,567 LINEARIZED OPTICAL DIGITAL-TO -ANALOG MODULATOR (Filed: 8/6/19 Pending)
   
   The above 10 patents and the pending application describe a system for converting digital data into a modulated optical signal. The digital-to-analog modulator includes an electrically controllable device having M actuating electrodes. The device outputs an optical signal that is modulated in response to binary input voltages applied to the actuating electrodes. The system also includes a digital-to-digital converter that provides a mapping of input data words of N bits to M actuation voltages and supplies the M actuation voltages to modulate the unmodulated optical stream. The M actuation voltages may be equal or larger in number than the number of bits N in each input data word. The digital-to-digital converter may also be enabled to map each digital input data word to an actuation voltage vector as a subset of all binary actuation vectors available, when M is greater than N to represent each of the input data words to linearize the optical output of the modulator. In embodiments included, in the patents and applications, the modulator provides amplitude and phase modulation capability to generate various modulation types including PAM modulation, I-Q (quadrature modulation) QAM modulation etc. as is well understood. The implementations discussed and claimed include use Mach-Zehnder modulators, Laser modulators or other types of optical modulators to achieve the various modulation types.

E-Marketing Recommendations

LOT IM-1

1. Patent # 8,429,160 User Preference Correlation for Web-based Selection (Filed: 10/12/2010 Issued: 4/23/2013)
   
   Enables e-Marketing Businesses to access up to 100x more online product reviews enabling richer and more productive recommendations for online shoppers, as well as earlier and more accurate suggestions shortly after a new product is introduced. For existing e-Marketing websites, the reviews for products are typically harvested only from the website making the offer. At the same time, there are much greater numbers of reviews for the same product and other products on other websites. To correlate these reviews requires the missing link covered by the claims in US Pat No 8,429,160. 
    

2.  Patent Application # 13/829,303 User Preference Correlation for Web-based Selection. (Filed: 3/14/2013)
   
   Pending CIP Application No 13/829,303 broadens the claims issued in Pat No 8,429,160, and adds description and claims for correlation using weighted preferences including mixes of positive and negative preferences.

High resolution methods for patterning deposition materials

LOT PS-2

1. Patent #9,227,220 Method for Patterning Materials on a Substrate
   (Filed 11/23/2012 Issued 01/05/2016)
   
   Electrostatic imaging of materials in solution using a patterning web having embedded electric charges. Includes alignment method and finishing options.
    

2. Patent #9,761,620 Method and System for Manufacturing using a Programmable Patterning Structure (Filed 09/19/2016 Issued 09/12/2017)
   
   Electronic programmability of each deposited layer leads to an agile manufacturing system. Configurable for imaging a gas, a liquid, or a powder. Refinement of alignment method.
    

3. Patent # 10,312,319 Programmable Charge Storage Arrays and Associated Manufacturing Devices and Systems (Filed 09/05/2017)
   
   New charge storage array achieves programmability using a simplified system, not requiring semiconductor wafers. Further refinement of alignment method. Configurable for building products using stacked molecular layers.

 

Low leakage, low sigma VT, low short channel effects

LOT SG-1

1. Patent #7,224,205 Apparatus and Method for Improving Drive-Strength and Leakage of Deep Submicron MOS Transistors (Filed 1/4/2005 Issued 5/29/2007)
   
   A method of reducing the leakage of deep submicron transistors by dynamically changing the threshold voltage by adjusting the transistor well voltage with a gate-connected poly-silicon diode.
    

2. Patent #7,375,402 Method and Apparatus for Increasing Stability of MOS Memory Cells (Filed 12/29/2004 Issued 5/20/2008)
   
   A deep sub-micron memory in which the threshold voltage of a row of cells is dynamically biased using a diode voltage divider comprising gate connected diode(s) and the well in which the access and pull-down transistors are situated.

LOT SG-2

1. Patent #8,994,123 A Variation Resistant Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) (Filed 3/20/2012 Issued 3/31/2015)
   
   An MOS transistor that minimizes threshold variations through the use of an undoped epitaxial channel within a recess having a controlled depth and controlled endwalls as a consequence of etching the recess through the drain extension structures. Threshold variations in this bulk device match those of FinFET and FDSOI.
    
    

2. Patent # 9,190,485 An Improved, Fluctuation Resistant FDSOI Transistor with Implanted Subchannel (Filed 7/25/2013 Issued 11/17/2015)
   
   A method of building a transistor with a low-temperature, recessed, undoped epitaxial channel. This method prescribes doing all the source/drain and source/drain extension implants prior to etching a recess. The etching of the recess is controlled by the sidewall spacers remaining after sacrificing a poly gate. Similarly, a subchannel implant is localized by the window defined by the sidewall spacers. The recess may be etched either before or after the subchannel doping is implanted. The resulting transistor is essentially free of threshold voltage fluctuations.
    

3. Patent # 9,263,568 Fluctuation Resistant Low Access Resistance Fully Depleted SOI
   Transistor with Improved Channel Thickness Control and Reduced Access Resistance (Filed 7/25/2013 Issued 2/16/2016)
   
   A silicon on insulator transistor having a channel region with the following characteristics: Sharply defined endwalls relative to the source and drain extensions, an undoped channel layer between 5 nm and 15 nm thick (thickness defined to minimize threshold fluctuations), and an extremely thin layer (δ-layer) of high doping to set the transistor threshold. These properties result in a transistor with extremely small σVT.
    

4. Patent #9,269,804 Gate Recessed FDSOI Transistor with Sandwich of Active and Etch Control Layers (Filed 7/25/2013 Issued 2/23/2016)
   
   A fully depleted, SOI transistor structure based on a bi-layer of single crystal Si over single crystal SiGe, or SiGe over Si. In the source and drain regions, both layers are doped appropriately for the transistor class, NMOS or PMOS. Within the channel region, the layer adjacent to the underlying backside oxide is exposed through differential etching, leaving an appropriately thin channel region with thicker, lower resistance source and drain regions, which may be further improved by a silicide layer.
    

5. Patent #9,312,362 Manufacture of a variation resistant metal-oxide-semiconductor field effect transistor (MOSFET) (Filed 3/20/2015 Issued 4/12/2016); (Divisional of US8,994,123)
   
   A method of fabricating a low σVT transistor by using a poly gate to define drain extension regions, the using sidewall spacers to define source and drain regions, depositing interlayer dielectric, then sacrificing the poly gate and etching a recess with controlled depth into the underlying well. This recess is filled with an un-doped epitaxial semiconductor, and the transistor is finished with a high-K gate dielectric, a metal gate and interconnect.
    

6. Patent #9,373,684 A Variation Resistant Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) (Filed 3/20/2012 Issued 6/21/2016)
   
   A method of fabricating a transistor with low σVT that starts with a poly gate that is used to define the extents of source and drain extension layers, and after the poly gate receives dielectric sidewalls, those sidewalls define the extent of the more heavily doped source and drain regions. The poly gate and its underlying oxide are etched away to create a recess with boundaries defined by the dielectric sidewalls. This recess provides an abrupt boundary with the source and drain extensions. The recess may be etched to contact an underlying buried layer, or its bottom may be filled with one or more highly doped epi layers. The recess is then filled with a channel epitaxial layer, which is essentially zero-doped, having a thickness between 5 and 15 nm. The transistor is finished with high-K gate dielectric, metal gate, and interconnect.

 

1. Application #WO 2013027092 A1 Variation resistant metal-oxide-semiconductor field effect transistor (MOSFET) (Filed 5/2/2012 Published 2/28/2013)
   
   An MOS transistor that minimizes threshold variations through the use of an undoped epitaxial channel within a recess having a controlled depth and controlled endwalls as a consequence of etching the recess through the drain extension structures. Threshold variations in this bulk device match those of FinFET and FDSOI.

 

1. Application # WO2013140199 A1 Variation resistant metal-oxide-semiconductor field effect transistor (MOSFET) (Filed 6/2/2012 Published 9/26/2013)
   
   A method of fabricating a low σVT transistor by using a poly gate to define drain extension regions, the using sidewall spacers to define source and drain regions, depositing interlayer dielectric, then sacrificing the poly gate and etching a recess with controlled depth into the underlying well. This recess is filled with an un-doped epitaxial semiconductor, and the transistor is finished with a high-K gate dielectric, a metal gate and interconnect.
    

LOT SG-3

1. Patent #9,012,276 Variation Resistant MOSFET with Superior Epitaxial Properties (Filed 7/3/2014 Issued 4/21/2015)
   
   A method of preparing a transistor with a low-temperature epitaxial channel within an etched recess employing a selective etch to establish <111> planes at the endwalls and sidewalls of the recess, promoting facet-free epitaxial growth.

 

1. Patent #9,379,214 Reduced Variation MOSFET Using a Drain-Extension-Last Process (Filed 2/9/2015 Issued 6/28/2016)
   
   A MOSFET having its source and drain regions spaced away from the gate, with the electrical connections to the channel established by a low-temperature epi layer deposited in a shallow recess after all other high temperature steps have been completed.
    

2. Patent 9,847,404 Fluctuation Resistant FinFET (Filed 9/11/2013 Issued 12/19/17)
   
   A FinFET having a composite channel region consisting of a core, which may be highly doped, and a sheath which is zero doped. The zero-doped sheath has an abrupt boundary with the source and drain extension regions of the transistor because it is epitaxially grown in a recess that was anisotropically etched into the originally thicker fin, using dielectric sidewalls for etch masking. The transistor is completed with high-K gate dielectric, a metal gate, and interconnections.
    

LOT SG-4

1. Patent Application # 15/226,118 REDUCED LOCAL THRESHOLD VOLTAGE VARIATION MOSFET USING MULTIPLE LAYERS OF EPI FOR IMPROVED DEVICE OPERATION. (Priority:8/3/2015; Filed 8/2/2016 pending)
    

A device structure with multiple layers of low temperature epitaxy is disclosed that eliminates source and drain and extension implants, providing a planar interface with abrupt junctions between epitaxial extensions and substrate, mitigating electrostatic coupling between transistor drain and transistor channel and reducing short channel effects. The reduction of channel doping results in improved device performance from reduced impurity scattering and reduction of random dopant induced threshold voltage variations (sigma-Vt). Avoiding implants further reduces device sigma-Vt due to random dopants’ diffusion from source and drain extensions, which creates device channel length variations during thermal activation anneal of implanted dopants. The defined transistor structure employs at least two levels of low-temperature epitaxy, and creates a planar interface with various types of transistor substrates resulting in performance improvement. Mixed epitaxial layer growth materials inducing tensile or compressive gate stresses can be advantageously used with the invention to further improve device characteristics.
 

LOT SG-5

1. Provisional Application #: 62/990,627 LOW ELECTROSTATIC FIELD TRANSISTOR (LEFD) USING SELECTIVE LOW TEMPERATURE EPITAXIAL SPACER (Filed: 3/17/2020 Pending)
    

A simplified device technology that can be implemented with a reduced number of masking and other process steps is proposed. The device structure reduces the effect of short channel effects on the operation of the devices developed and allow the devices to be scaled with minimum increase in device complexity. The processing is made much simpler by reduction or elimination of implant steps and associated high temperature activation/ drives but uses new available technology with lower temperature processing and selective epitaxial depositions. The replacement/ elimination of critical implant and activation steps reduce uncertainty of dopant location relative to the channel and help reduce the associated variability of device characteristics. The reduction in short channel effects and reduction in variability of device characteristics enable the devices to move down the device scaling and integration path. The disclosed device and technology are usable for device processing on planar semiconductor wafers, on Silicon on Insulator (SOI) and even for unique device structures like FinFET at and below the 28 nm device dimensions.
 

1. Provisional Application #: 62/989,658 FFT-DRAM (Filed:3/14/2020 pending)
    

A DRAM integrated with Flat Field Transistor device technology (FFT) and using the features of FFT is proposed. The Flat Field technology is implementable on bulk silicon or silicon-on-insulator substrates. It eliminates the impact of random dopant distributions on the threshold voltage (Vt) and reduces short channel effects in the MOS transistors. Hence the FFT transistors operate at lower supply voltages while maintaining the required noise margins. Tighter control of the Vt of MOS transistors can be used to improve drive currents and reduce leakage. The charge storage capacitor is integrated through the FFT’s source, above the surface of the silicon, using etched features, like trenches, holes, or fins to increase storage capacitance. The DRAM processing is integrated with the FFT process in the disclosed FFT-DRAM with a few additional steps.

Medical Imaging

LOT MI-1

1. Patent # 9,554,772. Non-Invasive Imager for Medical Applications. (Filed: 3/5/2014 Issued 1/31/2017)
   
   A method and process is described for providing Non-Invasive three dimensional (3-D) image of a patient such that during surgical or other procedures, the person performing the procedure can visually identify the organs and the location of the instruments in real time inside the body. Such a non-invasive imaging and reconstruction using spatially coordinated imaging in three dimensions is a very valuable tool especially to the surgical community. The high-powered computing capabilities, advances in the imaging techniques, individually or in combination when combined with noise filtering and error correction capabilities, have made accurate 3-D imaging in real time from scans a reality. These 3-D images are also used as a diagnostic tool, a practice tool and a teaching tool by the medical community. There may be other applications in these and related areas which may emerge as technology develops and they become apparent to individuals practicing the art.

 

Multi Core Processing

LOT MC-1

1. Patent Number: 6,738,837 Digital system with split transaction memory access Patent Date: 05/18/2004
   
   his patent improves the efficiency of the processor by enabling read and writes data to be stored in FIFOs as split access transaction memories. This allows more efficient use of the processor by enabling processing to take place while memory access over the bus takes place. This is part of the processor group, as it enhances the processor efficiency.
    

2. Patent Number: 6,351,806 RISC processor using register codes for expanded instruction set Patent Date: February 26, 2002
   
   This is a processor patent and falls in the processor block.
    

3. Patent Number: 6,647,450 Multiprocessor computer systems with command FIFO buffer at each target device Patent Date: November 11, 2003
   
   This patent relates to improving the processing efficiency of the processor unit by having commands stored in FIFOs between command bus and processor enabling faster sequential execution. This falls in the processor block.
    

4. Patent Number: 6,205,462 Digital multiply-accumulate circuit that can operate on both integer and floating-point numbers simultaneously Patent Date: March 20, 2001
   
   his is a patent in the ALU –handling multiply accumulate of integer and floating numbers in the same MAC. Hence this is in the ALU block. 
    

5. Patent Number: 7,043,518 : Method and system for performing parallel integer multiply accumulate operations on packed data Patent Date: May 9, 2006
   
   This is a patent in the ALU –handling simultaneous multiply accumulate of multiple integer numbers in a MAC. Hence this is in the ALU block. 
    

6. Patent Number: 7,716,269 Method and system for performing parallel integer multiply accumulate operations on packed data Patent Date: May 11, 2010
   
   This is a patent in the ALU –handling simultaneous multiply accumulate of multiple integer numbers in a MAC. Hence this is in the ALU block. 
    

7. Patent Number: 6,711,655 Finding available memory space by finding its associated memory transfer controller Patent Date: March 23, 2004
   
   This patent is a way of optimizing the operation of a memory controller by identifying available memory. This is part of the memory control block. 
    

8. Patent Number: 6,708,259 Programmable wake up of memory transfer controllers in a memory transfer engine Patent Date: March 16, 2004
   
   The patent is specific to enabling methods for waking up an idle memory transfer controller (MTC) in response to an event from an external source. This will hence fall in the memory control block.
    

9. Patent Number: 8,681,526 Size and retry programmable multi-synchronous FIFO Filing Date: July 2, 2008
   
   This is a DMA related patent that allows deadline-based scheduling of data transfer directly into processor memory. Hence it falls within the DMA block.
    

10. Patent Number: 9,032,104 Method and system for performing DMA in a multi-core system-on-chip using deadline-based scheduling Filing Date: September 3, 2013
    
    This is a memory patent that relate to a FIFO that is programmable for size and has transaction retry capability. It is also enabled by gray code based encode/ decode and synchronization circuit that is common for all FIFO sizes. FIFOs are used in multiple locations to facilitate orderly data transactions. The use includes IO blocks and other areas where temporary storage is needed. Since this is a memory type, it is also shown in the local memory block.
     

LOT MC-2

1. Patent Number: 6,874,049 Semaphores with interrupt mechanism Patent Date: March 29, 2005
   
   The patent is a means of identifying shared resources that are free and available for use by a processor, using semaphore method, without taking up a lot of bus cycles in identifying the availability. This is hence a bus arbitration method and is in the arbiter block.
    

2. Patent Number: 6,701,398 Global bus synchronous transaction acknowledge with non-response detection Patent Date: March 2, 2004
   
   Foreign: Japan This is a patent that relates to a global bus arbitration scheme for high speed buses that connect to multiple processing clusters. But it is implemented as part of the arbitration unit.
    

3. Patent Number: 6,810,455 Bus arbitration system and method for carrying out a centralized arbitration with independent bus request and grant lines Patent Date: October 26, 2004
   
   This patent refers to improved bus arbitration. Hence it is in the arbiter block.
    

4. Patent Number: 6,912,673 Bus analyzer unit with programmable trace buffers Patent Date: June 28, 2005
   
   This is a bus analyzer patent and is placed into the bus analyzer block.
    

5. Patent Number: 8,190,942 Method and system for distributing a global timebase within a system-on-chip having multiple clock domains Patent Date: May 29, 2012 
   
   This patent is a generic patent that describes a way to synchronize clocks on an SOC – it relates to clock distribution on chip. Hence, it is placed in the clock distribution and timing block. 
    

LOT MC-3

1. Patent Number: 6,212,591 Configurable I/O circuitry defining virtual ports Patent Date: April 3, 2001 Foreign: Japan
   
   This is an I/O related patent that allows configuring the I/O port to any size within the physical port width. This falls in the I/O section
    

2. Patent Number: 6,931,466 Reprogrammable input-output pins for forming different chip or board interfaces Patent Date: August 16, 2005
   
   This is a method for reconfiguring I/O pins for different applicable connections and fall in the I/O block.
    

3. Patent Number: 7,249,202 System and method for DMA transfer of data in scatter/gather mode Patent Date: 7/24/2007
   
   This patent relates to DMA operations using multiple buffers for data transfer.
    

4. Patent Number: 8,151,008 Method and system for performing DMA in a multi-core system-on-chip using deadline-based scheduling Patent Date: April 3, 2012.
   
   This is a DMA related patent that allows deadline-based scheduling of data transfer directly into processor memory. Hence it falls within the DMA block.
    

5. Patent Number: 6,836,869 Combined cyclic redundancy check (CRC) and Reed-Solomon (RS) error checking unit Patent Date: December 28, 2004 
   
   This patent is a generic patent that can be used in multiple areas. In the processor application error correction is used to check the incoming data. Hence it is included in the I/O block and the memory block. 
    

Networking

LOT NW-1

 

These five patents and one pending application relate to efficient networking using separately, Transmitted protocol information to identify next hop, identify and avoid network congestion etc.

 

Datalink frames or networking packets contain protocol information in the header and optionally in the trailer of a frame or a packet. We are proposing a method in which part of or all of the protocol information corresponding to a frame or a packet is transmitted separately in another datalink frame. The "Separately Transmitted Protocol Information" is referred to as STPI. The STPI contains enough protocol information to identify the next hop node or port. STPI can be used avoid network congestion and improve link efficiency. Preferably, there will be one datalink frame or network packet corresponding to each STPI, containing the data and the rest of the protocol information and this frame/packet is referred to as DFoNP. The creation of STPI and DFoNP is done by the originator of the frame or packet such as an operating system.

 

1. Patent #8,139,574 CREATION AND TRANSMISSION OF PART OF PROTOCOL INFORMATION CORRESPONDING TO NETWORK PACKETS OR DATALINK FRAMES SEPARATELY (filed: 8/18/2006 Issued: 3/20/2012)
    

A method implemented in hardware in a first network switch for switching Data Link frames, wherein said first network switch is used for interconnecting network nodes in a network, said method comprising: (a) receiving information required to identify at least one next hop node of a first Data Link frame in a second Data Link frame, wherein said second Data Link frame is received from a second network node, wherein said information and said first Data Link frame are transmitted separately by said second network node, wherein a next hop node of said first Data Link frame is a third network node to which said first Data Link frame is to be transmitted by said first network switch; (b) identifying said third network node before receiving said first Data Link frame by using said information required to identify at least one next hop node of said first Data Link frame, wherein said first Data Link frame is not used for identifying said third network node; (c) receiving said first Data Link frame from said second network node after identifying said third network node to which said first Data Link frame is to be transmitted; and (d) transmitting said first Data Link frame to said third network node
 

1. Patent #8,811,400 (Cont. 8,139,574) METHOD FOR IDENTIFYING NEXT HOP (filed 2/6/2012 Issued: 8/19/2014)
    

A method implemented in a first network apparatus used for forwarding network packets, wherein said first network apparatus is used for interconnecting network nodes in a network, said method comprising: (a) receiving information required to identify at least one next hop node of a first network packet, wherein said information is received by said first network apparatus from a second network node in a first data link frame, wherein said information and said first network packet are transmitted separately by said second network node, wherein said first data link frame does not contain said first network packet, wherein a next hop node of said first network packet is a third network node to which said first network packet is to be transmitted by said first network apparatus; (b) identifying said third network node before said first network packet is received by using said information required to identify at least one next hop node of said first network packet, wherein said first network packet is not used for identifying said third network node; (c) receiving said first network packet from said second network node after identifying said third network node to which said first network packet is to be transmitted; and (d) transmitting said first network packet to said third network node
 

1. Patent 9,479,442 (Cont. 8,811,400) Method for congestion avoidance (filed: 7/1/2014 Issued: 10/25/2016)
    

A method implemented in a first network apparatus used for forwarding network packets, wherein said first network apparatus is used for interconnecting network nodes in a network, said method comprising: a) receiving a first request; b) responding to said first request by transmitting at least one first network packet to a second network node before transmitting a second network packet to said second network node, wherein said at least one first network packet is to be transmitted out of a first network port in said second network node, wherein said second network packet is to be transmitted out of a second network port in said second network node, wherein network load on said first network port is less than network load on said second network port, wherein a set of network packets to be transmitted from said first network apparatus to said second network node comprises said at least one first network packet and said second network packet; and c) transmitting network packets in said set of network packets in a first order different from a second order in which network packets in said set of network packets were received by said first network apparatus
 

1. Patent #9,741,246 (Cont. 9,479,442) Method for congestion avoidance (filed:6/20/2016 Issued: 8/29/2017)
    

A method implemented in a first network apparatus used for forwarding network packets, wherein said first network apparatus is used for interconnecting network nodes in a network, said method comprising: a) receiving a first request; b) responding to said first request by transmitting at least one first network packet to a second network node before transmitting a second network packet to said second network node, wherein a first queue in said second network node is to be used for forwarding said at least one first network packet, wherein a second queue in said second network node is to be used for forwarding said second network packet, wherein network load on said first queue is less than network load on said second queue, wherein said at least one first network packet and said second network packet are to be transmitted out of said second network node, wherein a set of network packets to be transmitted from said first network apparatus to said second network node comprises said at least one first network packet and said second network packet; and c) transmitting network packets in said set of network packets in a first order different from a second order in which network packets in said set of network packets were received by said first network apparatus
 

1. Patent # 10,11,498 (Div. 9,479,442) Networking using PCI Express (filed: 9/19/2016 Issued: 10/23/2018)
    

 A method implemented in a first network apparatus used for forwarding network packets, wherein said first network apparatus is used for interconnecting network nodes in a network, wherein said first network apparatus uses PCI Express transactions for communicating to a PCI Express root bridge connected to it, said method comprising: a) receiving a first address of a network packet; b) using said first address of said network packet for reading said network packet from a second network node; c) receiving said network packet in a first PCI Express read completion from said PCI Express root bridge, wherein said first network apparatus behaves like a PCI Express end node; and d) writing said network packet to memory in destination node of said network packet, wherein destination node of said network packet is a third network node
 

1. Application #16/132,427 (pending cont. 10,11,498) Network Congestion and Packet Reordering. (filed:9/16/2018 Pub: 1/17/2019)
    

A method implemented in a first network apparatus used for forwarding data link frames, wherein said first network apparatus is used for interconnecting network nodes in a network, said method comprising: a) receiving a first request; b) responding to said first request by transmitting at least one first data link frame to a second network node before transmitting a second data link frame to said second network node, wherein a set of data link frames received by said first network apparatus comprises said at least one first data link frame and said second data link frame; and c) transmitting data link frames in said set of data link frames in a first order different from a second order in which data link frames in said set of data link frames were received by said first network apparatus.

 

Non-Volatile Flash Patents

LOT FM-1

1. Patent # 7,583,530 Multi-Bit Memory Technology (MMT) and Cells. (Filed: 10/2/2006 Issued: 9/2009)
   
   This patent discusses the method and structures for storing more than one bit in a cell – at differing locations using non-spreading storage medium. Multi-bit storage in a single memory cell is become the norm in the industry. The use of a Nitride layer or a silicon-nodule layer or similar layers capable of location specific charge storage with no spreading, allows easy implementation of multi-bit technology. If the charge is stored in the traps in the Nitride storage layer, an Oxide Nitride Oxide is used as the storage element. If charge is stored in layer of discrete silicon-nodules separated by a thin insulating film, an Oxide silicon-nodule Oxide storage element is used as the storage layer. The exemplary multi-bit cells proposed are programmed by hot electron programming and erased either by using high Voltage tunneling, or by use of a lower voltage MIM Metal-Insulator-Metal Diode carrier generation method and technology called the Tunnel-Gun or TG.
    

1. Patent # 7,376,014 HIGHLY RELIABLE NAND FLASH MEMORY USING FIVE SIDE ENCLOSED FLOATING GATE STORAGE ELEMENTS. (Filed: 8/18/2006 Issued: 5/20/2008)
   
   A NAND flash memory system with an array of individual charge storage elements, such as floating gates, arranged in a NAND string, each element being capable of selectively storing data in the form of charge there-in during a program or an erase operation, and during a read operation sensing the quantum of charge stored to provide reconstruction of data. Such a memory made with a floating gate that is spaced away from the diffusions and covered on all five sides except the channel side, by the control gate, there by having increased coupling with the associated advantage of lower high voltages, reduced impact of the unwanted disturb conditions, and providing for improved retention and reliability characteristics at higher operating temperatures is disclosed. The main emphasis in this technology is to provide a device with improved retention, endurance, and temperature characteristics meeting the Automotive specifications even with some area penalty.

 

One-time programmable memory having reduced cell size

LOT PS-3

1. Patent # 10,312,319 Programmable Charge Storage Arrays and Associated Manufacturing Devices and Systems (Filed 09/05/2017)
   
   Simplified charge storage cell does not require semiconductors; can be patterned with a single masking step such as E-beam. Programmed with multi-channel E-beam or another charged particle beam. Memory array may be used for patterning organic, inorganic, and biological materials over large areas, e.g. 1-meter x 1 centimeter in a roll-to-roll patterning system. Resolution of around 70 million dots per inch.

 

PCI Express Interconnect

LOT PE-1

1. Patent #8,189,603; PCI EXPRESS TO PCI EXPRESS BASED LOW LATENCY INTERCONNECT SCHEME FOR CLUSTERING SYSTEMS (File priority date:10-4-2005)
    

2. Patent #:9,519,608; (Cont. of 8,189,603) PCI EXPRESS TO PCI EXPRESS BASED LOW LATENCY INTERCONNECT SCHEME FOR CLUSTERING SYSTEMS (filed: 1/3/2015 Issued:12/13/2016)

3. Patent Application #: 15/175,800; (pending Cont. of 9,519,608) - PCI EXPRESS TO PCI EXPRESS BASED LOW LATENCY INTERCONNECT SCHEME FOR CLUSTERING SYSTEMS- Filed: 6/7/2016
    

The above three PCI Express based interconnect patents and pending application cover interconnection schemes using PCI Express protocols over PCI Express links for clustering stand-alone PCI Express based processing systems to make larger clusters of interconnected processing systems.

PCI Express is a Bus or I/O interconnect standard for use inside the computer or embedded system enabling faster data transfers to and from peripheral devices. The standard is still evolving but has achieved a degree of stability such that other applications can be implemented using PCIE as basis. A PCIE based interconnect scheme to enable switching and inter-connection between multiple PCIE enabled systems each having its own PCIE root complex, such that the scalability of PCIE architecture can be applied to enable data transport between connected systems to form a cluster of systems, is proposed. These connected systems can be any computing, control, storage or embedded system. The scalability of the interconnect will allow the cluster to grow the bandwidth between the systems as they become necessary without changing to a different connection architecture.

 

Semiconductor Packaging, Testing

LOT PS-1

1. Patent #7,427,809 Repairable Three-Dimensional Semiconductor Subsystem 
   (Filed 12/16/2004 Issued 9/23/2008)
   
   A semiconductor integration platform having an assembly layer comprising an array of wells formed on a semiconductor substrate, each well connected to a conductive trace and filled with conductive material. The array of wells is adapted to accept a component to be attached.
    

2. Patent #7,505,862 Apparatus and Method for Testing Electronic Systems
   (Filed 05/29/2004 Issued 03/17/2009)
   
   Describes a modern testing method that emphasizes operational functionality, captured by an on-board test chip. Includes method for learning correct system behavior, not requiring the traditional development of test vectors via logic simulation. Elimination of probes and cables improves the noise margin of the tester.

 

1. Patent # 7,535,107 Tiled Construction of Layered Materials
   (Filed 10/12/2005    Issued 05/19/2009)
   
   A tiled film construction enables diverse materials to be combined in a manner that allows advantageous materials to be utilized; for example, a low-k material like Cytop, while overcoming CTE mismatch.
    

Wireless Transceiver Patents

LOT TH-1

1. Patent # 7,010,330 Power Dissipation in Wireless Transceivers
   
   Methods and circuits for reducing power dissipation in wireless transceivers and other electronic circuits and systems. Embodiments of the present invention use bias current reduction, impedance scaling, and gain changes either separately or in combination to reduce power dissipation. For example, bias currents are reduced in response to a need for reduced signal handling capability, impedances are scaled thus reducing required drive and other bias currents in response to a strong received signal, or gain is increased and impedances are scaled in response to a low received signal in the presence of no or weak interfering signals
    

2. Patent #9,331,728 Power Dissipation Reduction in Wireless Transceivers
   
   Methods and circuits for reducing power dissipation in wireless transceivers and other electronic circuits and systems. Embodiments of the present invention use bias current reduction, impedance scaling, and gain changes either separately or in combination to reduce power dissipation. For example, bias currents are reduced in response to a need for reduced signal handling capability, impedances are scaled thus reducing required drive and other bias currents in response to a strong received signal, or gain is increased and impedances are scaled in response to a low received signal in the presence of no or weak interfering signals
    

1. Patent #9,838,962 Power Dissipation Reduction in Wireless Transceivers (filed 3/24/2016; Issued 12/5/2017)
   
   Processes, methods and circuits for improving battery life by reducing the battery power-drain of battery-powered devices with wireless receivers is disclosed. Embodiments provide for variably changing the bias current, impedance and gain through a plurality of values, either separately or in combination, during receiver circuit operation to optimize power dissipation. The dynamic changes to gain, bias and impedance characteristics of the receiver circuit may occur in any of an amplifier, a filter, and a mixer, and are responsive to the components of an input signal comprising a desired signal and interferer signal. Dynamic changes may also be made to a dynamic range and noise floor of the receiver circuit.
    

2. Patent #10,129,825 Power Dissipation Reduction in Wireless Transceivers (filed: 3/24/2016 Issued: 11/13/2018)
   
   Processes, methods and circuits for improving battery life by reducing the battery power-drain of battery-powered devices using wireless transceivers is disclosed. Embodiments of the present invention provides for dynamically changing the bias current, impedance and gain, either separately or in combination, during circuit operation to optimize or reduce power dissipation. The dynamic variations of gain, bias and impedance characteristics of mainly the receiver circuit are responsive to the components of an input signal comprising a desired signal and an interferer signal. The dynamic variations may be implemented by varying the value of a resistance and/or a capacitance by opening switches across one or more portions of the resistance. Also, the dynamic variations may include setting any of the gain, bias current, or impedance parameters of the receiver circuit in between a high and low level, followed by adjusting the parameter up or down in response to a desired signal and an interferer signal.
    

3. Patent #10,524,202 (Cont. 9,838,962) Power Dissipation Reduction in Wireless Transceivers (filed: 11/28/17 Issued: 12/31/19)
    

4.  Patent Application # 16/714,629 (Cont.9,838,962) Power Dissipation Reduction in Wireless Transceivers (filed: 12/13/19 - pending)

Methods and circuits for reducing power dissipation in wireless transceivers and other electronic circuits and systems. Embodiments of the present invention use bias current reduction, impedance scaling, and gain changes either separately or in combination to reduce power dissipation. For example, bias currents are reduced in response to a need for reduced signal handling capability, impedances are scaled thus reducing required drive and other bias currents in response to a strong received signal, or gain is increased and impedances are scaled in response to a low received signal in the presence of no or weak interfering signals.
 

LOT TH-2

1. Patent # 7,049,875 One-Pin Automatic Tuning of MOSFET Resistors
   
   Methods and apparatus for automatic tuning of MOSFET resistors providing accuracy and linearity throughout process and temperature variations. In accordance with the methods, the source and drain of a MOSFET device are biased in a balanced manner around a common mode voltage using a circuit controlling the gate voltage of the MOSFET to set the current through the MOSFET responsive to the value of a resistor. Operating MOSFETs, such as in MOSFET-C filters, with the same device conductivity type, gate bias, substrate voltage and signal common mode voltage provides linear MOSFET resistors, accurately set by a single resistance value. Use of an external resistor provides a single pin setting of MOSFET resistances, which may be independent of temperature and process variations. Various embodiments are disclosed
    

2. Patent # 7,075,377 Quadrature Voltage Controlled Oscillators with Phase Shift Detector
   
   In wireless application there is use of quadrature oscillators that generate signals that are capable of oscillating at quadrature of each other. The quadrature oscillator is comprised of two differential modified Colpitts oscillators. A capacitor bank allows for the selection of a desired frequency from a plurality of discrete possible frequencies. The quadrature oscillator is further coupled with a phase-error detector connected at the point-of-use of the generated `I` and `Q` channels and through the control of current sources provides corrections means to ensure that the phase shift at the point-of-use remains at the desired ninety degrees.
    

3. Patent # 7,155,185 Apparatus and Methods for Eliminating DC Offset in a Wireless Communication Device 
   
   Apparatus and methods for eliminating DC offset in a wireless communication device operable on a continuous basis or on a sampled basis. In a receive channel, the output of a forward variable gain amplifier is fed back to an RC circuit to charge the capacitor (C) to a voltage dependent on the DC offset in the variable gain amplifier output. The voltage on the capacitor is amplified and summed with the input to the variable gain amplifier. The RC circuit is configured to provide a high gain feedback at DC and very low frequencies, but very low gain at signal frequencies. Preferably the output of the forward variable gain amplifier is fed back to the RC circuit with a gain that is inversely proportional to the forward gain. Disconnection of the capacitor and feedback of the capacitor voltage provides sampled operation. Various embellishments and sample applications are disclosed
    

4. Patent # 7,253,712 Integrated High Frequency Balanced-to-Unbalanced Transformers
   
   Integrated high frequency balanced-to-unbalanced transformers suitable for operation in high frequencies, such as radio frequencies. Embodiments disclosed give consideration to issues related to the layout of the primary and secondary inductors for the minimization of capacitive effects between layers while using a minimal number of metal layers. Two solutions are provided, one having embodiments with a symmetrical primary inductor in a 4-metal layer implementation and one having embodiments with a non-symmetrical primary inductor in a 3-metal layer implementation
    

5. Patent # 7,268,627 Pre-Matching of Distributed and Push-Pull Power Transistors
   
   Pre-matching of distributed push-pull and power transistors enabling the effective use of high-power and high-frequency transistor arrays. In accordance with the invention, a pre-matching element is connected between stages of multi-transistor arrays. The pre-matching element serves to transform the impedance at a connecting point between stages toward an impedance level that is less sensitive to transmission line losses. In one embodiment of the invention the pre-matching element is a shunt inductor.
    

1. Patent # 7,271,622 Quadrature Voltage Controlled Oscillators with Phase Shift Detector
   
   In wireless application there is made use of a quadrature oscillators that generate signals that are capable of oscillating at quadrature of each other. The quadrature oscillator is comprised of two differential modified Colpitts oscillators. A capacitor bank allows for the selection of a desired frequency from a plurality of discrete possible frequencies. The quadrature oscillator is further coupled with a phase-error detector connected at the point-of-use of the generated `I` and `Q` channels and through the control of current sources provides corrections means to ensure that the phase shift at the point-of-use remains at the desired ninety degrees
    

2. Patent # 7,286,015 Linear-in-dB Variable Gain Amplifiers with an Adaptive Bias Current
   
   Linear-in-dB current-steering VGAs with an adaptive bias current operable so that as the gain of the amplifier decreases, the DC current consumption also decreases. The modified VGA circuits result in power consumption savings, which are of particular value in wireless (battery powered) applications.
    

3. Patent # 7,372,925 Wireless LAN Receiver with I and Q RF and Baseband AGC Loops and DC Offset Cancellation
   
   A wireless local area network receiver having separate automatic gain control (AGC) loops for providing a radio frequency AGC and a baseband frequency AGC, as well as a DC offset cancellation circuit. The AGC loops control a low noise amplifier amplifying the received RF signal, and the baseband signal or signals from a mixer of I and Q mixers. The DC offset compensation loop is also responsive to the baseband AGC signal to maintain a substantially fixed gain in the DC offset compensation feedback. Details of various embodiments are disclosed, including embodiments for orthogonal frequency division multiplexing (OFDM) that provide the AGC operation and the DC offset cancellation to the desired levels within the relatively short period of a preamble that precedes the data transmission.
    

4. Patent # 7,489,192 Low-noise Amplifiers
   
   A low-noise amplifier, that utilizes multiple monolithic transformer magnetic feedback to simultaneously neutralize the gate-drain overlap capacitance of the amplifying transistor and achieve high gain at high frequencies when driving an on-chip capacitance, is shown. The multiple transformer topology permits negative and positive feedback to be applied constructively, allowing for a stable design with adequate gain and large reverse isolation without Noise Figure degradation.
    

5. Patent # 7,499,687 Wireless Transmitter DC Offset Recalibration 
   
   In many circuits, including those operating in radio frequency (RF), there is commonly a need to perform DC offset cancellation. The DC offset is an error in an output signal in respect to the input that may cause a circuit to enter into undesirable or non-tolerable conditions of operation. While in most cases a static solution is provided the use of an analog loop may be inappropriate because of the adverse impact on speed. By adding a fast feedback loop finely impacting the adjustment of an amplifier, both the initial calibration is achieved as well as a recalibration of the system.
    

6. Patent # 7,546,332 Apparatus and Methods for Implementation of Mathematical Functions
   
   Apparatus and methods for implementation of mathematical functions apparatus providing both speed and accuracy. Disclosed are specific circuits and methods of operation thereof that may be used for the purpose of implementing an exponential function, a squaring function, and a cubic function, using the same basic circuit. By applying a desired weighting function on a current source, an output current provides a value that corresponds exactly to the desired mathematical functions at discrete points, and closely tracks values in between the discrete points. The precision is defined by the selection of a voltage reference for the circuit. Various embodiments are disclosed, as well as embodiments implementing other exemplary functions.
    

7. Patent # 7,554,397 Highly Linear Low-Noise Amplifiers
   
   A predistortion method for CMOS Low-Noise-Amplifiers (LNAs) to be used in Broadband Wireless applications is presented. The method is based on the nulling of the third order Intermodulation distortion (IMD3) of the main amplifier by a highly nonlinear predistortion branch. Maximum third order product cancellation is ensured by a transformer feedback method. The technique improves linearity in a wide range of input power without significant gain and Noise Figure (NF) degradation. Simulation results on a 1-V LNA indicate a 10.3 dB improvement in the Input Third-Order Intercept Point (IIP3) with a reduction of only 1 dB and 0.44 dB in amplifier gain and NF respectively.
    

8. Patent # 7,702,045 Method for Estimating Wireless Channel Parameters
   
   Method for the estimation of channel parameters in a wireless communication system. In accordance with the method several levels of the wireless channel parameters estimation take place to address the specific requirements of the channel. Based on the level of estimation required an appropriate estimation algorithm is selected to achieve the desired results. The evaluation of the channel state and thereafter determining the appropriate parameter estimation requirements provide for a superior overall performance of the wireless system.

LOT TH-3

1. Patent # 7,808,356 Integrated High Frequency BALUN and Inductors
   
   Integrated high frequency balanced-to-unbalanced transformers and inductors suitable for operation in high frequencies, such as radio frequencies. Embodiments disclosed give consideration to issues related to the layout of the top and bottom inductors for the minimization of capacitive effects between layers. A displacement between the conductive paths of the top inductor and the bottom inductor is shown that provides for superior performance over prior art solutions.
    

2. Patent # 8,183,970 Integrated High Frequency BALUN and Inductors
   
   Integrated high frequency balanced-to-unbalanced transformers and inductors suitable for operation in high frequencies, such as radio frequencies. Embodiments disclosed give consideration to issues related to the layout of the top and bottom inductors for the minimization of capacitive effects between layers and methods of manufacturing thereof. A displacement between the conductive paths of the top inductor and the bottom inductor is shown that provides for superior performance over prior art solutions.
    

3. Application # 8,275,338 A Passive High-Frequency Image Reject Mixer
   
   The apparatus is a complete passive implementation of an image reject mixer (IRM) that is capable of operating at very high frequency. Using a hybrid as part of the IRM circuit enables operation at very high frequencies that also employs a high intermediate frequency (IF). All the components of the design are passive and implementable in MOS technologies providing significant cost and implementation advantages. Furthermore, the apparatus is operative at frequencies that are higher than several tens of GHz.
    

4. Patent # 8,331,896 A Method of Operation of a Passive High-Frequency Image Reject Mixer
   
   A passive implementation of an image reject mixer (IRM), capable of operating at very high frequency, is operative according to the disclosed method. The IRM comprises a quad MOS multiplier and a lumped-element hybrid, resulting in a passive IRM. Operative at a radio frequency (RF) of tens of GHz with an intermediate frequency (IF) of several GHz. The RF+ and RF- signals are provided to two quad MOS multipliers. A local oscillator signal (LO) is used to provide LO+ and LO- signals to one of the multipliers and by providing the LO to a phase shifter, generated are a ninety degree shifted LO+ and LO- signals provided to the other multiplier. Providing the hybrids with the outputs of both multipliers and selecting an appropriate IF signal from each of the hybrids ensures the proper operation of the passive IRM.
    

5. Patent # 8,505,193 Method for manufacturing an on-chip BALUN transformer
   
   Integrated high frequency balanced-to-unbalanced transformers and inductors suitable for operation in high frequencies, such as radio frequencies. Embodiments disclosed give consideration to issues related to the layout of the top and bottom inductors for the minimization of capacitive effects between layers and methods of manufacturing thereof. The manufacturing process comprises forming of a first winding in a first metal layer; forming an insulating layer over at least the first metal layer; forming of a second winding in a second metal layer such that the second winding path has both a vertical and a horizontal displacement to the first conductive path, preferably with an overlap that is less than a full overlap; and forming shunts to ensure continuity of each of the first and second windings.
    

6. Patent # 8,805,316 Method of manufacture of a passive high-frequency image reject mixer 
   
   A passive implementation of an image reject mixer (IRM), capable of operating at very high frequency, is manufactured in a variety of silicon processes. The IRM comprises a quad MOS multiplier and a lumped-element hybrid, resulting in a passive IRM, operative at radio frequencies (RF) of tens of GHz with an intermediate frequency (IF) of several GHz. The RF+ and RF− signals are provided to two quad MOS multipliers. A local oscillator signal (LO) is used to provide LO+ and LO− signals to one of the multipliers and by providing the LO to a phase shifter, generated are a ninety degree shifted LO+ and LO− signals provided to the other multiplier. Providing the hybrids with the outputs of both multipliers and selecting an appropriate IF signal from each of the hybrids ensures the proper operation of the passive IRM.
    

7. Patent # 9,031,525 Method of manufacture of a passive high-frequency image reject mixer 
   
   A passive implementation of an image reject mixer (IRM), capable of operating at very high frequency, is manufactured in a variety of silicon processes. The IRM comprises a quad MOS multiplier and a lumped-element hybrid, resulting in a passive IRM, operative at radio frequencies (RF) of tens of GHz with an intermediate frequency (IF) of several GHz. The RF+ and RF− signals are provided to two quad MOS multipliers. A local oscillator signal (LO) is used to provide LO+ and LO− signals to one of the multipliers and by providing the LO to a phase shifter, generated are a ninety degree shifted LO+ and LO− signals provided to the other multiplier. Providing the hybrids with the outputs of both multipliers and selecting an appropriate IF signal from each of the hybrids ensures the proper operation of the passive IRM.