Lot SD-1

Low leakage, low sigma VT,  low short channel effects

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1. Patent #7,224,205   Apparatus and Method for Improving Drive-Strength and Leakage of Deep Submicron MOS Transistors  (Filed 1/4/2005     Issued 5/29/2007)
   
   A method of reducing the leakage of deep submicron transistors by dynamically changing the threshold voltage by adjusting the transistor well voltage with a gate-connected poly-silicon diode.
    

2. Patent #7,375,402   Method and Apparatus for Increasing Stability of MOS Memory Cells  (Filed 12/29/2004      Issued 5/20/2008)
   
   A deep sub-micron memory in which the threshold voltage of a row of cells is dynamically biased using a diode voltage divider comprising gate connected diode(s) and the well in which the access and pull-down transistors are situated.
    

3. Patent #7,586,155   Apparatus and Method for Improving Drive-Strength and Leakage of Deep Submicron MOS Transistors   (Filed 4/19/2007      Issued 9/8/2009)
   
   (Continuation in Part of US7,224,205)
   
   A transistor with low voltage operation enhanced by using one or more forward-biased diodes connected between the transistor’s gate and well, so that the well is biased to increase drive current in the ON condition, but returns to a low-leakage well bias in the OFF condition.

4. Patent #7,651,905   Apparatus and Method for Reducing Gate Leakage in Deep Sub-Micron MOS Transistors Using Semi-Rectifying Contacts    (Filed 4/19/2005      Issued 1/26/2010)
   
   A method of reducing the gate leakage in submicron SRAM devices by incorporating a double layer in the gate stack, one layer being poly-silicon of either N-type for NMOS or P-type for PMOS, and the second layer is either a metal or poly-silicon of the opposite doping, so the difference in work functions reduces the stress on the gate oxide without reducing the drive current.
    

5. Patent #7,683,433   Apparatus and Method for Improving Drive-Strength and Leakage of Deep Submicron MOS Transistors    (Filed 9/19/2006      Issued 3/23/2010)
   
   A transistor utilizing a forward biased gate-to-well diode to create dynamic control of the threshold voltage, giving a low threshold for high drive in the ON condition and a high threshold for low leakage for low leakage in the OFF condition, this transistor having a capacitor in parallel with the diode to assure rapid response under switching conditions.
    

6. Patent #7,691,702   A Method of Manufacture of an Apparatus for Increasing Stability of MOS Memory Cells    (Filed 4/24/2008      Issued 4/6/2010)
   
   A method of improving memory performance by incorporating a forward-biased diode of any type between the row access line and the isolated p-well that encloses the NMOS access transistors.  The diode and the well form a voltage divider providing dynamic control of the threshold voltage, for high conductance when accessing the memory cells and low leakage when isolating the cells.
    

7. Patent #7,863,689   An Apparatus and Method Thereof for Using a Well Current Source to Effect a Dynamic Threshold Voltage of a MOS Transistor  (Filed 1/5/2009      Issued 1/4/2011)
   
   This is a transistor with a floating well, connected to the gate with a Schottky diode paralleled with a capacitor.  Active transistors inject current into their wells, and this transistor uses this current to adjust the the well voltage for low VT during ON conditions and higher VT during OFF conditions.  This differential arises because when the transistor is ON, the injected current is passed through a PN junction, but when the transistor is OFF, the injected current passes through the Schottky, establishing a lower well voltage, leading to a higher VT.  The capacitor improves transient response.
    

8. Patent #7,898,297   Apparatus, Methods and Layout for Dynamic Threshold Voltage Control in MOS Transistors      (Filed 3/9/2007      Issued 3/1/2011)
   
   Dynamic logic circuit incorporating an adaptive threshold PMOS transistor for pre-charge, in which the threshold adaptation is effected by a passive circuit between the gate and isolated well of that PMOS.  The passive circuit incorporates one or more diodes which are forward biased when the PMOS is on, and it incorporates a capacitor paralleling the forward biased diode(s) for better transient response.
    

9. Patent #8,048,732   Apparatus and Method for Improving Drive-Strength and Leakage of Deep Submicron MOS Transistors Using a Fast Forward Capacitor      (Filed 2/8/2010      Issued 11/1/2011)
   
   (Continuation in Part of US7,683,433)
   
   Method for increasing drive current and reducing leakage current in an MOS transistor by connecting a parallel combination one or more forward biased diodes and capacitor between the gate of the transistor and its isolated well.
    

10. Patent #8,207,784   Method and Apparatus for MOSFET Drain-Source Leakage Reduction      (Filed 2/12/2009      Issued 6/26/2012)
    
    A leakage control circuit for logic circuits employing active transistor clamps to set a floating well potential to a voltage that increases drive current for the transistor in that well when it is turned ON and to set the well potential to ground or an alternative potential that minimizes leakage when that transistor is turned OFF.
     

11. Patent #8,247,840   Apparatus and Method for Improving Drive-Strength and Leakage of Deep Submicron MOS Transistors for SOI Devices      (Filed 1/5/2009      Issued 8/21/2012)
    
    (Continuation in Part of US7,224,205)
    
    A silicon-on-insulator structure utilizing a new connection method to apply voltages to the underside of the transistor, and these voltages are derived by using one or more forward biased diodes between the gate and the underside of the SOI transistor, forming a voltage divider.
     

12. Patent #9,135,977   Random Access Memories with an Increased Stability of the MOS Memory Cells      (Filed 4/24/2008      Issued 9/15/2015)
    
    (Divisional application from US7,375,402)
    
    An SRAM cell incorporating one or more forward-biased diodes connected between the word line and an isolated P-well containing NMOS access and pull-down transistors, and forming a voltage divider with the P‑well, so that its voltage is dynamically changed in such a way that the NMOS transistors have a low threshold voltage when accessed, but a higher threshold voltage when not accessed.
     

13. Patent #9,147,459   Dynamic and Non-Volatile Random Access Memories with an Increased Stability of the MOS Memory Cells    (Filed 11/2/2009      Issued 9/29/2015)
    
    (Divisional application from US9,135,977)
    
    A DRAM array incorporating one or more forward-biased diodes connected between the word line and an isolated P-well containing NMOS access transistors, and forming a voltage divider with the P-well, so that its voltage is dynamically changed in such a way that the NMOS transistors have a low threshold voltage when accessed, but a higher threshold voltage when not accessed.
     

14. Patent # EP 1831932   Apparatus and method for improving drive strength, leakage and stability of deep submicron MOS transistors and memory cells     (Filed 12/28/2005      Issued 3/24/2010)
    
    (European patent based on US7,375,402, US9,135,977 and US9,147,459, but it may have lapsed for non-payment of dues.)
    
    MOS transistor with an isolated well and one or more series connected poly-silicon diodes connected between the transistor’s gate and the well, forming a voltage divider that changes the voltage on the well to provide a low threshold voltage when the transistor is turned ON and a high threshold voltage when the transistor is turned OFF.  The claims also include the structure above as a method for increasing the transistor drive current and decreasing its leakage.
     

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1. Patent #8,994,123   A Variation Resistant Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET)      (Filed 3/20/2012      Issued 3/31/2015)
   
   An MOS transistor that minimizes threshold variations through the use of an undoped eptitaxial channel within a recess having a controlled depth and controlled endwalls as a consequence of etching the recess through the drain extension structures.  Threshold variations in this bulk device match those of FinFET and FDSOI.
    

2. Patent #9,012,276   Variation Resistant MOSFET with Superior Epitaxial Properties     (Filed 7/3/2014      Issued 4/21/2015)
   
   A method of preparing a transistor with a low-temperature  epitaxial channel within an etched recess employing  a selective etch to establish <111> planes at the endwalls and sidewalls of the recess, promoting facet-free epitaxial growth.
    

3. Patent # 9,190,485   An Improved, Fluctuation Resistant FDSOI Transistor with Implanted Subchannel      (Filed 7/25/2013      Issued 11/17/2015)
   
   A method of building a transistor with a low-temperature, recessed, undoped epitaxial channel.  This method prescribes doing all the source/drain and source/drain extension implants prior to etching a recess.  The etching of the recess is controlled by the sidewall spacers remaining after sacrificing a poly gate.  Similarly, a subchannel implant is localized by the window defined by the sidewall spacers.  The recess may be etched either before or after the subchannel doping is implanted.  The resulting transistor is essentially free of threshold voltage fluctuations.
    

4. Patent # 9,263,568   Fluctuation Resistant Low Access Resistance Fully Depleted SOI
   Transistor with Improved Channel Thickness Control and Reduced Access Resistance      (Filed 7/25/2013      Issued 2/16/2016)
   
   A silicon on insulator transistor having a channel region with the following characteristics:  Sharply defined endwalls relative to the source and drain extensions, an undoped channel layer between 5 nm and 15 nm thick (thickness defined to minimize threshold fluctuations), and an extremely thin layer (δ-layer) of high doping to set the transistor threshold.  These properties result in a transistor with extremely small σVT.
    

5. Patent #9,269,804   Gate Recessed FDSOI Transistor with Sandwich of Active and Etch Control Layers      (Filed 7/25/2013      Issued 2/23/2016)
   
   A fully depleted, SOI transistor structure based on a bi-layer of single crystal Si over single crystal SiGe, or SiGe over Si.  In the source and drain regions, both layers are doped appropriately for the transistor class, NMOS or PMOS.  Within the channel region, the layer adjacent to the underlying backside oxide is exposed through differential etching, leaving an appropriately thin channel region with thicker, lower resistance source and drain regions, which may be further improved by a silicide layer.
    

6. Patent #9,312,362   Manufacture of a variation resistant metal-oxide-semiconductor field effect transistor (MOSFET)      (Filed 3/20/2015      Issued 4/12/2016)
   
   (Division of US8,994,123)
   
   A method of fabricating a low σVT transistor by using a poly gate to define drain extension regions, the using sidewall spacers to define source and drain regions, depositing interlayer dielectric, then sacrificing the poly gate and etching a recess with controlled depth into the underlying well.  This recess is filled with an un-doped epitaxial semiconductor, and the transistor is finished with a high-K gate dielectric, a metal gate and interconnect.
    

7. Patent #9,373,684   A Variation Resistant Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET)      (Filed 3/20/2012      Issued 6/21/2016)
   
   A method of fabricating a transistor with low σVT that starts with a poly gate that is used to define the extents of source and drain extension layers, and after the poly gate receives dielectric sidewalls, those sidewalls define the extent of the more heavily doped source and drain regions.  The poly gate and its underlying oxide are etched away to create a recess with boundaries defined by the dielectric sidewalls.  This recess provides an abrupt boundary with the source and drain extensions.  The recess may be etched to contact an underlying buried layer, or its bottom may be filled with one or more highly doped epi layers.  The recess is then filled with a channel epitaxial layer, which is essentially zero-doped, having a thickness between 5 and 15 nm.  The transistor is finished with high-K gate dielectric, metal gate, and interconnect.
    

8. Patent #9,379,214   Reduced Variation MOSFET Using a Drain-Extension-Last Process     (Filed 2/9/2015      Issued 6/28/2016)
   
   A MOSFET having its source and drain regions spaced away from the gate, with the electrical connections to the channel established by a low-temperature epi layer deposited in a shallow recess after all other high temperature steps have been completed.
    

9. Application #2015/0008490     Fluctuation Resistant FinFET      (Filed 9/11/2013      Published 1/8/2015)
   
   A FinFET having a composite channel region consisting of a core, which may be highly doped, and a sheath which is zero doped.  The zero-doped sheath has an abrupt boundary with the source and drain extension regions of the transistor because it is epitaxially grown in a recess that was anisotropically etched into the originally thicker fin, using dielectric sidewalls for etch masking.  The transistor is completed with high-K gate dielectric, a metal gate, and interconnections.
    

10. Application #2016/0260816      Reduced Variation MOSFET Using a Drain-Extension-Last Process    (Filed 5/16/2016      Published 9/8/2016)
    
    (Division of US 9,379,214)
    
    A method for fabricating a MOSFET having its source and drain regions spaced away from the gate, with the electrical connections to the channel established by a low-temperature epi layer deposited in a shallow recess after all other high temperature steps have been completed.
     

11. Application #WO 2013027092 A1      Variation resistant metal-oxide-semiconductor field effect transistor (MOSFET)      (Filed 5/2/2012      Published 2/28/2013)
    
    An MOS transistor that minimizes threshold variations through the use of an undoped eptitaxial channel within a recess having a controlled depth and controlled endwalls as a consequence of etching the recess through the drain extension structures.  Threshold variations in this bulk device match those of FinFET and FDSOI.
     

12. Application # WO2013140199 A1    Variation resistant metal-oxide-semiconductor field effect transistor (MOSFET)      (Filed 6/2/2012      Published 9/26/2013)
    
    A method of fabricating a low σVT transistor by using a poly gate to define drain extension regions, the using sidewall spacers to define source and drain regions, depositing interlayer dielectric, then sacrificing the poly gate and etching a recess with controlled depth into the underlying well.  This recess is filled with an un-doped epitaxial semiconductor, and the transistor is finished with a high-K gate dielectric, a metal gate and interconnect.

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