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Electronic Packaging

Lot PS-1
Semiconductor Packaging, Testing, Cooling, Rework
  1. Patent #7,586,747 Scalable Subsystem Architecture having Integrated Cooling Channels
    (Filed 07/27/2006   Issued 09/08/2009)

    Scalable electronic subsystems built from stackable modules having a ball grid array (BGA) interface at the bottom of the stack. Re-workability is enabled, and optional cooling channels can be utilized between copper layers.


  2. Patent #7,535,107 Tiled Construction of Layered Materials
    (Filed 10/12/2005    Issued 05/19/2009)

    A tiled film construction enables diverse materials to be combined in a manner that allows the attractive properties of diverse materials to be utilized; for example, a low-k material like Cytop, while overcoming CTE mismatch.


  3. Patent #7,505,862 Apparatus and Method for Testing Electronic Systems
    (Filed 05/29/2004    Issued 03/17/2009)

    Structural testing with a test chip located on the system board. Method for learning correct system behavior, not requiring the traditional development of test vectors via logic simulation. Elimination of probes and cables improves the noise margin of the tester.


  4. Patent # 7,254,024 Cooling Apparatus and Method (Filed 04/08/2005    Issued 08/07/2007)

    A microblade is constructed within a copper foil jacket, can be aggressively cooled in a tank of circulating fluid. The microblade contains a miniaturized electronic assembly that may produce a lot of heat.


  5. Patent # 7,408,258 Interconnection Circuit and Electronic Module Utilizing same
    (Filed 02/20/2004    Issued 08/05/2008)

    Modules having copper substrates, 10GHz operation, imprinting method, cooling fluid, liquid cooled supercomputer.


  6. Patent # 7,163,830 Method for Temporarily Engaging Electronic Component for Test
    (Filed 12/07/2004    Issued 01/16/2007)

    An array of wells is provided on a substrate, each well filled with liquid metal. Used for producing known good die (KGD), system level test, burn-in, high-speed functional testing. Conductive bumps or mesas on the component under test are inserted into the liquid metal in the wells.

Please address any inquiries about the above patents to:

Dr. Demetris Paraskevopoulos
Managing Director
Nif/T, LLC
New Business Architects

11237 Mesa Circle, Reno, NV 89511


Phone - +1.775.376.1468

Email   -


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