Computing

Lot MC-1
Please address any inquiries about the above patents to:

Dr. Demetris Paraskevopoulos
Managing Director
Nif/T, LLC
New Business Architects

19160 Bainter Ave., Los Gatos, CA 95030

 

Phone - 408.395.2160
Fax     -  408.395.2161
Email   - info@nif-t.net

 

Multi Core Processing

 

  1. Patent Number: 6,738,837  Digital system with split transaction memory access  Patent Date: 05/18/2004

    his patent improves the efficiency of the processor by enabling read and writes data to be stored in FIFOs as split access transaction memories.  This allows more efficient use of the processor by enabling processing to take place while memory access over the bus takes place. This is part of the processor group, as it enhances the processor efficiency.
     

  2. Patent Number: 6,351,806   : RISC processor using register codes for expanded instruction set   Patent Date: February 26, 2002

    This is a processor patent and falls in the processor block.
     

  3. Patent Number: 6,647,450   : Multiprocessor computer systems with command FIFO buffer at each target device  Patent Date: November 11, 2003

    This patent relates to improving the processing efficiency of the processor unit by having commands stored in FIFOs between command bus and processor enabling faster sequential execution. This falls in the processor block.
     

  4. Patent Number: 6,205,462   : Digital multiply-accumulate circuit that can operate on both integer and floating point numbers simultaneously  Patent Date: March 20, 2001

    his is a patent in the ALU –handling multiply accumulate of integer and floating numbers in the same MAC. Hence this is in the ALU block. 
     

  5. Patent Number: 7,043,518    : Method and system for performing parallel integer multiply accumulate operations on packed data  Patent Date: May 9, 2006

    This is a patent in the ALU –handling simultaneous multiply accumulate of multiple integer numbers in a MAC. Hence this is in the ALU block. 
     

  6. Patent Number: 7,716,269  : Method and system for performing parallel integer multiply accumulate operations on packed data   Patent Date: May 11, 2010

    This is a patent in the ALU –handling simultaneous multiply accumulate of multiple integer numbers in a MAC. Hence this is in the ALU block. 
     

  7. Patent Number: 6,711,655   : Finding available memory space by finding its associated memory transfer controller  Patent Date: March 23, 2004

    This patent is a way of optimizing the operation of a memory controller by identifying available memory.  This is part of the memory control block. 
     

  8. Patent Number: 6,708,259  Programmable wake up of memory transfer controllers in a memory transfer engine  Patent Date: March 16, 2004

    The patent is specific to enabling methods for waking up an idle memory transfer controller (MTC) in response to an event from an external source. This will hence fall in the memory control block.
     

  9. Patent Number: 8,681,526  Size and retry programmable multi-synchronous FIFO   Filing Date: July 2, 2008

    This is a DMA related patent that allows deadline based scheduling of data transfer directly into processor memory.  Hence it falls within the DMA block.
     

  10. Patent Number: 9,032,104  Method and system for performing DMA in a multi-core system-on-chip using deadline-based scheduling  Filing Date: September 3, 2013

    This is a memory patent that relate to a FIFO that is programmable for size and has transaction retry capability. It is also enabled by gray code based encode/ decode and synchronization circuit that is common for all FIFO sizes.  FIFOs are used in multiple locations to facilitate orderly data transactions.  The use includes IO blocks and other areas where temporary storage is needed.  Since this is a memory type, it is also shown in the local memory block.   

 

  1. Patent Number: 6,874,049  Semaphores with interrupt mechanism  Patent Date: March 29, 2005

    The patent is a means of identifying shared resources that are free and available for use by a processor, using semaphore method, without taking up a lot of bus cycles in identifying the availability. This is hence a bus arbitration method and is in the arbiter block.
     

  2. Patent Number: 6,701,398  Global bus synchronous transaction acknowledge with non-response detection  Patent Date: March 2, 2004

    Foreign:  Japan This is a patent that relates to a global bus arbitration scheme for high speed buses that connect to multiple processing clusters. But it is implemented as part of the arbitration unit.
     

  3. Patent Number: 6,810,455  Bus arbitration system and method for carrying out a centralized arbitration with independent bus request and grant lines  Patent Date: October 26, 2004

    This patent refers to improved bus arbitration. Hence it is in the arbiter block.
     

  4. Patent Number: 6,912,673   Bus analyzer unit with programmable trace buffers  Patent Date: June 28, 2005

    This is a bus analyzer patent and is placed into the bus analyzer block.
     

  5. Patent Number: 8,190,942  Method and system for distributing a global timebase within a system-on-chip having multiple clock domains   Patent Date: May 29, 2012 

    This patent is a generic patent that describes a way to synchronize clocks on an SOC – it relates to clock distribution on chip.  Hence, it is placed in the clock distribution and timing block. 
     

  1. Patent Number: 6,212,591   Configurable I/O circuitry defining virtual ports  Patent Date: April 3, 2001   Foreign:  Japan

    This is an I/O related patent that allows configuring the I/O port to any size within the physical port width. This falls in the I/O section
     

  2. Patent Number: 6,931,466  Reprogrammable input-output pins for forming different chip or board interfaces  Patent Date: August 16, 2005

    This is a method for reconfiguring I/O pins for different applicable connections and fall in the I/O block.
     

  3. Patent Number: 7,249,202  System and method for DMA transfer of data in scatter/gather mode   Patent Date: 7/24/2007

    This patent relates to DMA operations using multiple buffers for data transfer.
     

  4. Patent Number: 8,151,008  Method and system for performing DMA in a multi-core system-on-chip using deadline-based scheduling  Patent Date: April 3, 2012

    This is a DMA related patent that allows deadline based scheduling of data transfer directly into processor memory.  Hence it falls within the DMA block.
     

  5. Patent Number: 6,836,869   Combined cyclic redundancy check (CRC) and Reed-Solomon (RS) error checking unit  Patent Date: December 28, 2004 

    This patent is a generic patent that can be used in multiple areas. In the processor application error correction is used to check the incoming data. Hence it is included in the I/O block and the memory block. 
     

PCI Express  Interconnect

  1. Patent #8,189,603;  PCI EXPRESS TO PCI EXPRESS BASED LOW LATENCY INTERCONNECT SCHEME FOR CLUSTERING SYSTEMS ( File priority date:10-4-2005)

  2. Appln #:14/588,937; (Cont. of 8,189,603) Allowed on 5/14/2016;  PCI EXPRESS TO PCI EXPRESS BASED LOW LATENCY INTERCONNECT SCHEME FOR CLUSTERING SYSTEMS

  3. Appln #:13/441,883; (Cont. of #8,189,603)  PCI EXPRESS TO PCI EXPRESS BASED LOW LATENCY INTERCONNECT SCHEME FOR CLUSTERING SYSTEMS

  4. Appln #: 15/175,800; (Cont. of 14/588,937 )  PCI EXPRESS TO PCI EXPRESS BASED LOW LATENCY INTERCONNECT SCHEME FOR CLUSTERING SYSTEMS

The above four PCI Express based interconnect applications cover interconnection schemes using PCI Express protocols over PCI Express links for clustering stand-alone PCI Express based processing systems to make larger clusters of interconnected processing systems.

PCI Express is a Bus or I/O interconnect standard for use inside the computer or embedded system enabling faster data transfers to and from peripheral devices. The standard is still evolving but has achieved a degree of stability such that other applications can be implemented using PCIE as basis. A PCIE based interconnect scheme to enable switching and inter-connection between multiple PCIE enabled systems each having its own PCIE root complex, such that the scalability of PCIE architecture can be applied to enable data transport between connected systems to form a cluster of systems, is proposed. These connected systems can be any computing, control, storage or embedded system. The scalability of the interconnect will allow the cluster to grow the bandwidth between the systems as they become necessary without changing to a different connection architecture.

Lot MC-2
Lot MC-3
Lot PE-1
 
 

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