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Semiconductor Devices - Test
Lot SD-1
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Dr. Demetris Paraskevopoulos
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Lot SD-2
Apparatus and Method for Improving Drive-Strength and Leakage of Deep Submicron MOS Transistors
Patent #7,224,205 (Filed 1/4/2005 Issued 5/29/2007)
A method of reducing the leakage of deep submicron transistors by dynamically changing the threshold voltage by adjusting the transistor well voltage with a gate-connected poly-silicon diode.
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